We would like to inform you about some major new developments in the teaching materials provided for Altera's DE2 Development and Education board. We hope that you have had a chance to experiment with your DE2 board, or perhaps have gone ahead and established a teaching laboratory using this board at your school.
Since we introduced the DE2 board earlier this year, DE2 teaching laboratories have been set up at more than 100 universities. DIGITAL LOGIC TEACHING MATERIAL In the summer of 2006 we released a comprehensive set of tutorials and laboratory experiments for use in digital logic courses. The tutorials have been written with a sophomore student in mind. They include step-by-step instructions and explain how to use Altera's Quartus II software with the DE2 board. The laboratory experiments span all of the important concepts in a digital logic course. They are designed to provide a strong learning experience that encourages students to create and test small circuits, and then use these proven designs to build larger, more interesting projects. We provide illustrative solutions, protected by passwords given only to registered instructors, in both VHDL and Verilog HDL for all of these experiments.
To make it easy for instructors to combine Altera's teaching material with their own, we provide the source files of the text collate utf8unicodeci and figures used in the laboratory descriptions. This material can be found at COMPUTER ORGANIZATION and EMBEDDED SYSTEMS TEACHING MATERIAL We have launched the first installment of our teaching material for computer organization and/or embedded systems courses, which makes use of the Nios II processor. We provide tutorials that introduce the Nios II instruction set architecture and show how to use the Quartus II software and its SOPC Builder tool to create embedded systems. We also provide the Altera Debug Client utility which allows students to easily compile, assemble, download and debug programs written in either the Nios II assembly language or in the C language. The Debug Client allows the user to explore how the programs are executed by the processor. It displays the contents of the processor registers and system memory, and includes features such as single-step execution, breakpoints and program trace.
We have also released a set of five laboratory experiments (with more to be provided over the next three months) on the topics that include basic computer system concepts, program-controlled I/O (polling), subroutines and stacks, interrupts, and bus communication. Illustrative solutions to these experiments are available to instructors under password protection. We are confident that this teaching material will enhance the usefulness of the DE2 board in the teaching environment and make it easy to create a rewarding laboratory experience for the students. To learn more, please visit EMBEDDED PERIPHERALS IP CORES Over the next couple of months we will be completing the release of a library of SOPC Builder components (IP cores) for all of the I/O devices on the DE2 board.
These components can be used as part of the SOPC Builder tool in the Quartus II software. They allow students to easily create Nios II systems that can access all of the I/O devices on the DE2 board.
We will also provide associated software drivers that can be incorporated into an Altera Debug Client project (or an Altera Nios II IDE project), and will provide several example projects using the software. A detailed schedule for the release of these IP cores is shown at the end of this message. The currently-available components in the library, and release notes for them, can be downloaded from FINAL REMARKS If you wish to request additional DE2 boards, please visit our Board Donation or Board Purchase web pages, which an be reached from Sincerely, University Program Team: Prof.
Stephen Brown, Blair Fort, Mike Phipps, Ralene Marcoccia, and Prof. Zvonko Vranesic P.S.
The SOPC Builder component release schedule is shown below. The IP library will be installed into the SOPC Builder's component directory. After the library is installed, you can find these IP cores in SOPC Builder in the component list under the “University Program DE2 Board” group. Documentation for the IP cores can be found in the Window’s START-Altera- Altera University Program IP Cores menu, or by right-clicking on the component in SOPC Builder and opening the “Data Sheet”.
Getting Started Professors and course instructors can register as of our University Program to:. Request donations of boards and software/IP licenses. Purchase hardware at reduced prices. Obtain complete solutions for our laboratory excercises.
Access Intel® FPGA and Enroll your students into one of our. Also, check our schedule and come see us in person. Course Material We provide teaching material specifically designed by professors for courses covering digital Logic, computer organization and embedded systems.
A Flash Memory is a non-volat ile type of memor y that can be electrical ly erased and reprogram med. It is simila r to volatile types of memory, such as SRAM and DRAM, in that it can be written to and read; however, it is different in that it retains its data even when the memory device is powered down.
The ability to retain its data makes it useful in applications such as Secur e Data cards and USB memor y sticks for the purposes of storing and transporti ng data. While flash memory is vers atile it has its limitat ions. Unlike volat ile memory, to change the memor y contents the data present in the memory must first be erased and only then can new data be written. The underlying technology also places a limitation on the number of times data can be written reliably to any particular location of the flash memor y.
T ypicall y, flash memory devic es allow each memor y location to be written in the order of 10000 times, and up to 100000 in high-end parts. The Altera University Program (UP) Flash Memory IP Core is a hardware component that facilitates the use of flash memory dev ices present on the Altera DE1 and DE2 boards. W e provide this core for general use, howeve r we advise that the flash memory not be used for temporary data storage, as doing so may significantly reduce the lifetim e of the flash memory chips. This document describes how to instantiate the Altera UP Flash Memory IP Core in an System-on-Programmable- Chip (SOPC) Builde r based design as well as a standal one module in user designs. To be exe cuted first.
2017 Repair Program Flash Memory
Doing so is inadvis able, because the new data cannot be guarante ed to be stored correc tly. More specifically, any bit that has been set to 0 cannot be changed to a 1 without using the memory location first. To protect the flash memory devices from accidental misuse, the Altera UP Flash Memory IP Core includes a protection mechanism that prevents writing data to non-empty memory locations. Any attempt to do so will result in the circuit behav ing as though the operation succee ded. Howe ver, no data will actual ly be writte n to the specified memor y locatio n. A subseq uent read operation will show that the memor y contents remain unchanged. SOPC Builder Flash Memory IP Core with Avalon Interconnect Interface.
This module is similar to the standalone version of the core, except in how it interfaces with a user circuit. In this cas e, the inte rf ace is fac ilit ate d by the A va lon Int erc onne ct fa bric.
The A va lon Int erc onne ct fab ric allo ws com pone nts to be attached to a system and assigns an address range for each device on the interconnect. Thus, a Nios II soft-core processor that connects to peripheral devices by the means of this interconnect, can access each device as a memory mapped slave, simply by providing the appropriate address to the Avalon Interconnect.
The Altera UP Flash Memory IP Core has two memory-mapped slave ports that connect to the Avalon Interconnect.
Overview Cyclone® V SoC and Arria® V SoC support the following flash devices both as a boot source and for mass data storage:. Quad serial peripheral interface (QSPI) flash. NAND flash. Secure Digital (SD), Secure Digital High Capacity (SDHC), Secure Digital eXtended Capacity (SDXC), MultiMediaCard (MMC), or Embedded MMC (eMMC) flash When choosing a flash device to incorporate with SoCs, it is important to consider the following:. Will the device work with the Altera® device BootROM?.
The hard processor system (HPS) can only boot from flash devices supported in the BootROM. Is the device verified to work and supported by software, such as the Preloader, U-Boot, and Linux?. Flying free don besig pdf editor. For supported devices, Altera provides the Preloader, U-Boot, and Linux.
software. For other devices, this software must be developed by the user. Is the device supported with the HPS Flash Programmer?. The HPS Flash Programmer enables writing to flash using a JTAG connection. This is primarily intended for programming the initial pre-loader or bootloader image. If the device is not supported by the HPS Programmer, other flash programming methods may be used, such as using the HPS to program flash.
For example, the flash programming capabilities of U-Boot can be used. Based on the criteria above, the following categories of flash devices are identified:.
Altera Tested and Supported Flash Device - These devices meet the criteria listed above. These devices receive regression testing with Altera tools and their use is fully supported by Altera Technical Support. Known to Work Flash Devices - These devices are not explicitly supported in the Altera tools, but have been known to work with SoCs. Many of these devices are programmed using U-Boot as an alternate programming method, but source changes to U-Boot might have to be made by users in order to configure a specific device. Incompatible Flash Devices - These devices will not work with Cyclone V SoC and Arria V SoC. The following sections present the support level for various flash devices for Cyclone V SoC and Arria V SoC. Quad SPI Flash Devices The quad SPI flash devices have the following advantages:.
Reliability: they typically support a minimum of 100,000 erase cycles per sector and a minimum of 20 years data retention. As a result, their management is simpler, with no need for error correction and bad block management. Low pin count requirement: a quad SPI flash device typically requires six pins, but it can be used with as few as four pins. High bandwidth A quad SPI flash device typically has smaller storage capacity than other flash devices. They are therefore mostly used as a boot source and not for mass storage. Up to four quad SPI flash chip selects can be used with Cyclone V SoC and Arria V SoC. The device will boot from quad SPI flash connected to chip select zero.
The current list of tested and supported devices is presented below. Note that the device list applies only to the HPS Quad SPI controller, and does not apply for FPGA configuration. NAND Flash Devices The main advantage of the NAND flash devices is large storage capacity. The disadvantages of NAND flash devices include:.
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A high pin count requirement (a minimum of 15 pins are required). More difficult to manage, as individual bit reliability is lower compared to quad SPI flash, error correction, and bad block management are required. Lower maximum bandwidth as compared to quad SPI flash devices The NAND flash devices are typically used for mass data storage, but they can also be used as a boot source.
The NAND flash devices to be used with Cyclone V SoC and Arria V SoC must satisfy at least the following requirements:. ONFI 1.0 compatibilty.
x8 interface. Single-level cell (SLC) or multi-level cell (MLC). Only one ce# and only one rb# pin. Page size: 512 bytes, 2 KB, 4 KB or 8 KB. Pages per block: 32, 64, 128, 256, 384, or 512. Error correction code (ECC) sector size can be programmed to 512 bytes (for 4, 8, or 16 bit correction) or 1,024 bytes (for 24 bit correction) The current list of tested and supported devices is presented below. Part Number Manufacturer Capacity Support Category Notes MTFC16GJDDQ-4M IT Micron 16 GB Known to Work eMMC v4.51 compliant MTFC16GAKAENA-4M IT Micron 16 GB Known to Work eMMC v5.0 compliant MTFC16GAKAEDQ-AIT Micron 16 GB Known to Work eMMC v5.0 compliant MTFC8GACAANA-4M IT Micron 8 GB Known to Work eMMC v4.51 compliant MTFC8GACAEDQ-AIT Micron 8 GB Known to Work eMMC v5.0 compliant S40410081B1B2W000 Cypress 8 GB Known to Work eMMC v4.51 compliant S40410161B1B2W010 Cypress 16 GB Known to Work eMMC v4.51 compliant.
To program your own design into the CFI flash memory device on the Arria® 10 Development Kit, use the following procedure. When using Windows version of the Quartus® Prime software, open the Nios® II command shell. Create a.flash file from a.sof for your own design. Refer to buildfactoryreadme.txt which you can find in the folder where you installed the Arria 10 GX FPGA Package for the development kit. Factoryrecovery buildfactorysource 2b. There are example commands to convert a.sof to a.flash file. Execute one of those commands according to your target area to program your design.
Replace file names with your file names when executing the commands. Program the.flash file. Set up the board with the default settings according to the Arria 10 FPGA Development Kit User Guide.
Connect a USB cable to the on-board USB Blaster II or an external USB Blaster II cable to JTAG header. Run the Quartus Prime Programmer. Program the following board update portal design to the Arria 10 device. Examples boardupdateportal a10fpgabup.sof 3e. Execute the following command on Nios II command shell nios2-flash-programmer -base=0x00000000.flash To configure your own design image by reconfiguration, use the following procedure. Set your board with the default settings following the instructions in the Default Switch and Jumper Settings section of Arria 10 FPGA Development Kit User Guide Arria 10 FPGA Development Kit User Guide locates it in the following path. Documents uga10fpgadevkit.pdf 2.
Power up your board 3. Push image select push button (S5) to select your own design image. Program LED 2:0 (D12,D13,D14) indicates which image is selected. Push program configuration push button (S6) to load the selected image to FPGA When your own design image is located in the factory image area or user hardware1 area, it can be configured at power-up using the following procedure.
Set your board with the default settings following the instructions in the Default Switch and Jumper Settings section of Arria 10 FPGA Development Kit User Guide except for load selector switch (SW6.4). Set the load selector switch (SW6.4) 2a. When your own image is located in factory image area, set SW6.4 to ON 2b. When your own image is located in user hardware1 area, set SW6.4 to OFF 3. Power up your board Note that the above procedure assumes the MAX® V device on the board contains the factory default system cotroller design and the CFI flash memory device has the factory default memory map.